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Showing posts from May, 2020

Faster Atanua

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I sped up Atanua so that it now takes 5 minutes to do 1/25 of a second, not 30+. What I actually speeded up was my own composite emulator. It could be made to go even faster but my video card doesn't support rendering to a Texture so the texture has to be uploaded at every change which is very slow.

ACE3NOKB V0.1 is off to China.

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The latest update has been ordered, for very slow delivery. This version includes some fixes identified with the last version but also some changes. Firstly the 3 74xx383s have been replaced with 2 *74xx4040. See https://github.com/ricaflops/Jupiter-II .The Memory map reverted back to original as far as RAM is concerned. ROM space 5k added overlapping the write-only. https://www.tindie.com/products/tynemouthsw/minstrel-4th-z80-computer-kit/ Other minor changes including adding power and ground lines to the KIO out, which meant adding 2 more pins to each and beefing up the power input socket. I also changed some of the fiddlier components to a larger size to make construction easier and moved one of the RAM chips to the back of the board, as it is an SMD device it caused no problems. The board is overall 1 cm deeper than before to accommodate the larger sockets. portions of char RAM and none decoded 3k for a total 5k extra. https://www.tindie.com/products/tynemouthsw/minstrel-4

Composite Logic

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I decided to test the logic for the composite system on the simulator Atanua, as I did for the RAM chip select, I had to add a few enhancements to Aranua to do it, the upgraded version is here . Atanua is designed around binary emulation so creating a composite signal was impossible so the emulator has a few more inputs to indicate the VSync and HSync pulses which are normally done by dropping the signal to zero compared with a normally higher value for background black. On hardware, this 34-minute video would run in 1/25 of a second. The logic does not start with a VSync so the first full image is not actually valid. The 2nd redraw shows the full extent of the screen. The red and green sections show the various sync pulses. The image output is scaled to the window so as the image grows you will see some scaling down.

It is only logical

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After the problems detailed in the last post I'm doing some more exhaustive testing of the select logic this time, as I've not only fixed the last problem, I hope but also changed the memory map so that the new space is in a different place. Here it is flashing away as it ticks through in 1k chunks.

ACE3NOKB V0 is a dud

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I got the board altogether and there are some unfixable faults on it. There was 1 fixable which is the large kludge to the left of the board. That was because I misaligned the bus going into the IC so all that is to shift it 1 place left. The more subtle problem is to do with the Chip Select on the video RAM. The system works by defaulting to having both ICs selected, this is done by pulling the CS pins low, this allows the Video circuitry access continually, it cuts down the time needed to access the chip but may put the power consumption up, which explains some hot running. The only times these pins are pulled high is when the CPU is accessing one of the video chips, when that happens the one not being accessed goes high. Anyway, I missed that trick and so the Video circuits could not access the RAM, other than that the worked a had a nice stable pattern. So I've now fixed that in design V0.1 which will soon be off to China, I've also taken the opportunity to change the