The Ace Place

It has been a while. Full-time paid employment means I have enough cash to finish this but limits the time I can spend finishing it. The current state of play it that I have added some SMDs to get in some practice with those. One of the SMDs is a frequency multiplier so that with the original crystal to drive the video I can vary the CPU speed from the 3.278MHz of the original ACE up to 19.668MHz and perhaps beyond. I've also made some modifications to make the KIO optional and enable full ACE compatibility. The KIOs are very difficult to get hold of and with Z84C15 and Z182 available these seem like the best CPU to be going forward. The fastest CPU I have is 20MHz and while I had to up the speed of the RAM, everything else seem happy on the CPU side. The Video was less happy, but I am not 100% convinced that was a speed problem. The multiplier I'm using on this board is a Renesas 512MLF , which is pin compatible with the On Semiconductor NB3N502DR2G , though the multiplicat...

After giving the previous idea some thought I've decided to change it. Instead of having a single 8k block at the top of memory that can be paged the same space will be occupied by 2 4k blocks. This will allow coying between blocks at a much greater rate. The first design I came up with uses a pair of 74AHCT573 Octal TransparentD-TypeLatchesWith 3-State Outputs one for each of the 4K blocks. It is a little clunky and has some annoying selection logic which adds time to the selection, each one is set with the top 8-bit of the address of the memory in the large chip but the ICs required are cheap and easily available. The second version uses 2 SN74LS670N 4-BY-4 REGISTER FILES WITH 3-STATE OUTPUTS each one holds 4 bits of the address of the large memory, the selection logic greatly simplified in that there isn't any. The ICs are not available in AHCT which I'd like, they are available at great expense in HCT at £5.65 and a far more reasonable £1.87 for LS, which is a...

While I'm waiting for the ACE3 board to comeback I thought I'd have a look at my plans for ACE4. This should include pageable RAM, the costs of RAM mean it is more expensive to fit the small RAM chips than go for a bigger one. While the Z180 has a fully-fledged MMU which can address up to 1 megabyte and map it, I'm going for something a bit simpler and that is to have the top 8k pageable. The circuit above is my current thinking. It should work as follows. For the bottom 56k, the #PAGED8K line should be high, this will force chip Z106, a SN74AHCT541N , active, which will put the normal A13, A14 and A15 address lines on to the memory chip bus(MA) while pulling MA16-20 low, thereby addressing the bottom 56k directly. If however #PAGED8K is low the chip Z105, a SN74AHCT574N ,  will be active and it will place on lines MA13-20 the data previously written to the chip, this will mean that any of the memory in the RAM chip can be accessed via this 8k block even that mapped to...

In addition to the cut down ACE2NOKB   design, I've also created something a bit closer to the original in ACE1 though it uses real keyboard switches. It has the edge connectors and only the changes need to make the output composite compatible and to cope with a lower impedance speaker. Though I have not built it the core of the system is the same keyboardless version. It should be compatible with all the hardware packs. The ICs are all in approximately the correct position, though the routing has no connection to the original.