Composite Logic
I decided to test the logic for the composite system on the simulator Atanua, as I did for the RAM chip select, I had to add a few enhancements to Aranua to do it, the upgraded version is here.
Atanua is designed around binary emulation so creating a composite signal was impossible so the emulator has a few more inputs to indicate the VSync and HSync pulses which are normally done by dropping the signal to zero compared with a normally higher value for background black.
On hardware, this 34-minute video would run in 1/25 of a second. The logic does not start with a VSync so the first full image is not actually valid. The 2nd redraw shows the full extent of the screen. The red and green sections show the various sync pulses.
The image output is scaled to the window so as the image grows you will see some scaling down.
Atanua is designed around binary emulation so creating a composite signal was impossible so the emulator has a few more inputs to indicate the VSync and HSync pulses which are normally done by dropping the signal to zero compared with a normally higher value for background black.
On hardware, this 34-minute video would run in 1/25 of a second. The logic does not start with a VSync so the first full image is not actually valid. The 2nd redraw shows the full extent of the screen. The red and green sections show the various sync pulses.
The image output is scaled to the window so as the image grows you will see some scaling down.
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