Beyond ACE 3

While I'm waiting for the ACE3 board to comeback I thought I'd have a look at my plans for ACE4. This should include pageable RAM, the costs of RAM mean it is more expensive to fit the small RAM chips than go for a bigger one. While the Z180 has a fully-fledged MMU which can address up to 1 megabyte and map it, I'm going for something a bit simpler and that is to have the top 8k pageable.
The circuit above is my current thinking. It should work as follows. For the bottom 56k, the #PAGED8K line should be high, this will force chip Z106, a SN74AHCT541N, active, which will put the normal A13, A14 and A15 address lines on to the memory chip bus(MA) while pulling MA16-20 low, thereby addressing the bottom 56k directly.
If however #PAGED8K is low the chip Z105, a SN74AHCT574N,  will be active and it will place on lines MA13-20 the data previously written to the chip, this will mean that any of the memory in the RAM chip can be accessed via this 8k block even that mapped to lower 56k or occupied by ROM or Video RAM. To set the data in the Z105 the CPU performs a write to port 0xFD this should pull the #PAGING line low and enable the Z105 load. From then on when the top 8k of memory is access the appropriate 8k in the RAM chip should be accessed.
The Schematics in KiCAD are available here.


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