New MMU

After giving the previous idea some thought I've decided to change it. Instead of having a single 8k block at the top of memory that can be paged the same space will be occupied by 2 4k blocks. This will allow coying between blocks at a much greater rate.
The first design I came up with uses a pair of 74AHCT573 Octal TransparentD-TypeLatchesWith 3-State Outputs one for each of the 4K blocks. It is a little clunky and has some annoying selection logic which adds time to the selection, each one is set with the top 8-bit of the address of the memory in the large chip but the ICs required are cheap and easily available.


The second version uses 2 SN74LS670N 4-BY-4 REGISTER FILES WITH 3-STATE OUTPUTS each one holds 4 bits of the address of the large memory, the selection logic greatly simplified in that there isn't any. The ICs are not available in AHCT which I'd like, they are available at great expense in HCT at £5.65 and a far more reasonable £1.87 for LS, which is almost the same speed but with higher power consumption.
With the addition of a couple of and gates, the circuit could be configured to have 4 blocks of 4K at the top of memory.
For the first solution, some extra or gates where need this required an extra logic chip is required also the ICs are 20 pins so it takes up a fair amount of extra PCB space for little or no gain. Conveniently both solution would look the same from a software point of view so if you cannot get the chips for one solution then use the other.


For the current version see https://github.com/flypie/Ace-2019/tree/master/KiCad/ACE4NOKB

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