Bah Humbug


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CPLDs & Xilinx

One of the problems with GALs is the development tools which are way out of date. Though preparing the files by hand doesn't seem to be too difficult. The other problem is the relatively small number of pins. The next step up is  Complex Programmable Logic Devices ; CPLDs come in a far larger variety and there or some development kits available for the older legacy designs.    Some of Microchips' offerings, such as the ATF1504AS, can be programmed using WinCUPL like GALS. They also offer a full system such as ATF15XX-DK3-U that can be bought from the likes of Mouser at reasonable prices, though it is quite a high value for reasonable. Lattice & Intel also do similar things.   Having done a bit of research and found that Xilinx has released their old Integrated Synthesis Environment; ISE system, which does schematic capture. I decided to check out that route. Schematic capture is not used that much, but, I find it very useful when translating the logic designed i...
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Interrupted

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It has been a while. Full-time paid employment means I have enough cash to finish this but limits the time I can spend finishing it. The current state of play it that I have added some SMDs to get in some practice with those. One of the SMDs is a frequency multiplier so that with the original crystal to drive the video I can vary the CPU speed from the 3.278MHz of the original ACE up to 19.668MHz and perhaps beyond. I've also made some modifications to make the KIO optional and enable full ACE compatibility. The KIOs are very difficult to get hold of and with Z84C15 and Z182 available these seem like the best CPU to be going forward. The fastest CPU I have is 20MHz and while I had to up the speed of the RAM, everything else seem happy on the CPU side. The Video was less happy, but I am not 100% convinced that was a speed problem. The multiplier I'm using on this board is a Renesas 512MLF , which is pin compatible with the On Semiconductor NB3N502DR2G , though the multiplicat...
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VGA

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I've been trying to work out what the highest rez I can fit into my Jupiter Ace Clone. After a bit of messing around, I think I can use a 4k dual-ported RAM paged into a 1K window for 80x51 chars with 8x8 chars. The underlying resolution would be 640x408 but not pixel addressable. This is my first bash at a schematic. It's right at the limit of speed capabilities for 7400 logic and memory at 25.2 Mhz. So it got a type of buffer/cache that I think I remember seeing in a hardware lecture many years ago. Any comments? See PDF of Schematic or  a Git on GitHub . Various people have commented that I'm being a bit pessimistic with the timings and that the chances of the chips taking the maximum time outlined in their specifications. Without the chips to test and measure, there is little chance of getting optimal performance. One thing this has made me do is to overcome my avoidance of GALs and other programmable logic. The one clear thing is that the tools available are a pain....
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