Interrupted

It has been a while. Full-time paid employment means I have enough cash to finish this but limits the time I can spend finishing it.

The current state of play it that I have added some SMDs to get in some practice with those. One of the SMDs is a frequency multiplier so that with the original crystal to drive the video I can vary the CPU speed from the 3.278MHz of the original ACE up to 19.668MHz and perhaps beyond.

I've also made some modifications to make the KIO optional and enable full ACE compatibility. The KIOs are very difficult to get hold of and with Z84C15 and Z182 available these seem like the best CPU to be going forward.

The fastest CPU I have is 20MHz and while I had to up the speed of the RAM, everything else seem happy on the CPU side. The Video was less happy, but I am not 100% convinced that was a speed problem.

The multiplier I'm using on this board is a Renesas 512MLF, which is pin compatible with the On Semiconductor NB3N502DR2G, though the multiplications are a little different, it is cheaper and possible out of production.

Not only is it handling the multiplication but also the conversion of the crystal output to TTL levels.

One problem did become apparent while testing this. Part of my tests code's output has always been a little strange, but I didn't worry too much, but at the higher speeds the ACE ROM developed similar issues. It turns out this was due to the way the interrupts are generated every 50th of a second.

The Z80 INT line is pulled low during the vertical blanking interval produced as part of the video circuitry. It is held low throughout the entire blanking. The Z80's maskable interrupts are level triggered, while the NMI is edge triggered.

For the normal ACE this isn't a problem as the interrupt handler takes longer to run than the blanking period. However, my test code has a very short handler and at high speeds the ACE handler finishes while the interrupt line is still low. So as soon as interrupts are enabled, the handler is called again. This causes problems as it means the internal clock can be increments more than 50 times a second.

To get around this, I needed to make the interrupt edge triggered.

When the INT line drops low to signal an interrupt, the Z80 issues an acknowledgment, which is ignored by the ACE hardware, this is also true of other designs. The signal is that the M1 line and the IOREQ line are pulled low.

So to make the INT process edge triggered first the transition needs to be detected, and the INT line pulled low and when the acknowledgment signal is detected the INT line can be pulled high. This will prevent multiple handler calls during vertical blank.

After a bit of head scratching, I produced this.

Which worked 1st time, when I actually got the breadboarding correct. The line from the video circuitry, V_SYNC_PULSE(50Hz), goes high to signal an interrupt. These means we can lose an invert from that circuit. This is detected on the clock pin of the flip-flop, which sets the flip-flops state low.
When the acknowledges is received by M1 & IOREQ lines going low, the flip-flop is then set to 1. This is regardless of the current state of V_SYNC_PULSE(50Hz) as the clock uses edge detection.

I've had a bit of a nightmare getting hold of the 74AHCT/ACT74 SMD's for the build, they have variously got lost in the post or simply not been dispatched. So what should have been finished a week ago still hasn't started.

If this works as planned, I'll be testing the audio and tape circuits to finish off the Mk3 version of the build before moving on to the Mk4 with dual ported RAM and a Z84C15. The main reason for the Mk4 is to enable the Mk5 using a Z180 which can run at 32MHz,